Technical Field
The present description relates generally to gate driver circuits for a half bridge or full bridge output driver stage.
Description of the Related Art
Recently in the market of integrated high voltage drivers the need for high frequency signals is growing. In order to reach high performance, high slew rate and low latency in the chip between the low voltage input and the high voltage output have to be addressed.
In DC-DC Converters applications high slew rate edges help to obtain higher efficiency because they lower commutation losses, hence they reduce the power consumption and increase the performance of systems that use those circuits. Moreover, a higher frequency allows smaller inductances to be chosen, this meaning higher efficiency and system lower costs.
In Envelope Tracking applications, high frequency signals allow having a proper supply voltage envelope. In these systems, the supply voltage has to be continuously adapted to the load request, in order to allow having maximum efficiency of the system. This is particularly suitable for digital communication base-stations (mobile phones and also digital television are the main examples). Moreover, as long as fast reaction to the output level has to be addressed, also a low latency from digital low voltage input signal to analog high voltage output signals across the power stage has to be obtained.
In electromedical applications and in particular in ecographic machines, high voltage half bridges are required to drive the piezoelectric element to obtain an ultrasound wave. High current peaks are required.
All these characteristics have usually to be reached through dedicated design solutions.
In FIG. 1, in order to better understand the problems of half bridges or full bridges driver output stages operating with a high slew rate signal, it is shown a half bridge driver 11 comprising a high side, i.e., the side connected to the power supply voltage, branch and a low side, i.e., the side connected to the lower reference voltage, in particular ground, branch. The half bridge 11 includes a high side output transistor, in particular a high voltage pMOS or pMOSFET Mp, and a low side output transistor, in particular a nMOS or nMOSFET Mn, which are controlled through respective gate drivers 10p and 10n, which drive gate signals Gp and Gn applied to their respective gate electrodes. Each of the gate drivers 10p and 10n receives as input a respective low level signal pLV or nLV, which is however referred to a high voltage ground, i.e., it is a shifted low level signal, in FIG. 1 being shown only a waveform LSC schematizing the transient oscillation causing a logic state change in the input low signal pLV on the high side gate driver 10p. Each of the gate drivers 10p and 10n is connected to a respective high voltage supply VPP for the high side or VNN for the low side and receives also a respective reference ground voltage referred to the respective high voltage supply voltage, VPP_RIF=VPP−VDD voltage or VNN_RIF=VNN−VDD voltage, VDD being the digital supply voltage, in particular the low level supply voltage.
With the reference 12 is indicated a parasitic inductance of a bonding wire, connecting the chip with a package pad 13, between the half bridge 11 and the high side high voltage supply VPP, and it is also indicated a voltage generator 14 associated to the package pad 13. With 15 is indicated a parasitic capacitance of the high side power MOSFET Mp, while with 16 are indicated capacitors representing capacitances existing between the supply line and the signal lines and between signal line and fixed voltages in the chip, and between the referred ground voltage VPP_RIF and fixed voltages in the chip. As already mentioned, for simplicity's sake, only parasitic elements corresponding to the high side are shown in FIG. 1, although dual parasitic elements are present in the low side.
With OLV is then indicated the overvoltage on the low voltage components relative to supply voltages VPP and reference ground voltage VPP_RIF, OV indicates a overvoltage on the signal on the gate of the high side MOSFET transistor Mp, UV a corresponding undervoltage, while OHV indicates a total overvoltage on the high voltage components at the output of the half-bridge 11. I indicates the spike of the current flowing in the high side MOSFET Mp, causing the VPP oscillations.
The parasitic elements 15 and 16 determine several effects in presence of high slew rate signals.
In the first place, high slopes on the output of a half-bridge driver cause the current spike I profile to have huge peaks. This current spikes, flowing through any metal path presenting parasitic inductance 15, such as bonding wires 12 and other bonding wires in the package, cause high oscillation on the supply voltages, which could:                damage the related power-stage MOSFET Mp or Mn with exceeding gate source voltage Vgs when the MOSFET is in the ON state, with exceeding drain source voltage Vds when the MOSFET is OFF state,        damage the low voltage logic        cause spurious turning-on or turning-off of the power device,because of a logic state change such as the one shown in signal LV at the gate driver 11p. This could cause damage of the power stage due to cross conduction (high Side and low Side simultaneously ON) and could cause the half bridge to be in a high impedance state.        
Several approaches have been taken in order to avoid the above indicated negative effects.
For instance, in order to obtain a low latency it is known to use a capacitive gate driver. This solution per se however determines sensitivity to high voltage supply oscillations. To avoid this latter problem it is known to reduce the parasitic inductances in the path, from the circuit to the filtering capacitance, for example by substituting bonding wires with bump bonding, although the results are usually not sufficient.
Also filtering the supply voltage with capacitance in the package or at a very small distance from the silicon usually turns out to be not sufficient. Further passive components in the package mean increased costs.
It is also known to split the supply path to the filtering passive components and to the generator. However, the bumps number and external passive components number increase, while a low area efficiency is obtained (bump-Limited silicon area and production costs)
Of course, also a slow turn-on and turn-off can be attempted with a lower working frequency and slew rate, but this determines limited functionalities, i.e., high propagation delay in the chip.
With regard to the problem of the spurious turn-on and turn-off, it is known to use a resistive level shifter which however is not always effective and causes high power consumption and slow commutations. A mask circuit instead is not applicable when several half bridges share the same power supply.